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IEEE

Vectorized Implementation of Kyber and Dilithium on 32-bit Cortex-A Series

Abstract: In the field of Post-Quantum Cryptography (PQC), which typically demands more memory and relatively lower performance compared to Elliptic-Curve Cryptography (ECC), recent studies have been ...
IEEE

Designing and Implementation of 32-bit 5 stage Pipelined MIPS based RISC Processor Capable of Resolving Data Hazards

Abstract: The main objective is to design and implement a 5-stage pipelined 32-bit High performance RISC Processor with MIPS architecture which is also capable in detecting and resolving Data Hazards.