Semiconductor Engineering

Context-Aware SPICE Simulation Improves The Fidelity Of ESD Analysis

Electrostatic discharge (ESD) is a major reliability concern for integrated circuit (IC) designs. ESD verification is proving to be a significant challenge at advanced nodes, due to growing IC design ...
Business Wire

New Advanced SPICE Model for ESD Diodes Addresses Challenges in IC Design and Protection

AUSTIN, Texas--(BUSINESS WIRE)--The Silicon Integration Initiative Compact Model Coalition is proud to announce the release of the ASM-ESD diode model, a new electrostatic discharge compact modeling ...
Electronic Design

Charged Device Model (CDM) ESD Testing: Getting a Clearer Picture

Of all of the component-level ESD tests available, the charged-device model (CDM) test is the closest to simulating real world events. CDM testing simulates ESD charging followed by a rapid discharge, ...
Semiconductor Engineering

Assessing ESD Sensitivity Of Interface IP Using Charged Device Model

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, especially from the completion of the silicon wafer processing to when the device is assembled ...
Business Wire

Apache Introduces PathFinder, the Industry’s First Full-chip ESD Physical Integrity Solution

SAN JOSE, Calif.--(BUSINESS WIRE)--Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced PathFinder™, a ...
EDN

Transistor level ESD verification in large SoC designs

When it comes to large system-on-chip (SoC) designs, there is a need for a comprehensive electrostatic discharge (ESD) verification flow that can verify both topological and geometrical constructions ...
EDN

FA leads to proper ESD tests

At our company, we used failure analysis (FA) to successfully determine what caused GaAs RF ICs to fail during retesting. In our case, the source of the damage turned out to be just as important as ...
Electronic Design

What’s The Difference Between HBM, CDM, And MM Test?

This file type includes high resolution graphics and schematics when applicable. EOS and ESD may be caused by the user’s application due to a transient, excessive supply current, poor grounding, low ...
Design-Reuse

Apache Introduces PathFinder, the Industry's First Full-chip ESD Physical Integrity Solution

San Jose, Calif. – May 10, 2010 – Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced PathFinder™, a ...